RE: regarding Mantis issue #3386

From: Yuri Tsoglin <yurit@cadence.com>
Date: Wed Jun 25 2014 - 07:37:11 PDT
I believe that for anything other than HDL objects it's simply irrelevant.
Unlike SystemVerilog (which is based on Verilog in the first place), e is not based on HDL language, and as such it doesn't have at all the notion of x and z values for its native expressions.


From: darren.galpin@infineon.com [mailto:darren.galpin@infineon.com]
Sent: Wednesday, June 25, 2014 17:29
To: Yuri Tsoglin; ieee1647@eda.org
Subject: RE: regarding Mantis issue #3386

I would agree, apart from I think that the intent behind the original ballot feedback this came from was that it would apply to anything, not just HDL objects.

Cheers,

Darren

From: owner-ieee1647@eda.org [mailto:owner-ieee1647@eda.org] On Behalf Of Yuri Tsoglin
Sent: Wednesday, June 25, 2014 3:22 PM
To: ieee1647@eda.org
Subject: regarding Mantis issue #3386

Hi,

Mantis issue #3386 is suggesting the following:

Consider adding wildcard equiality operators ==? and !=? like in SystemVerilog, where x and z values act as wildcard.

However, it seems that it's already in the standard.
Section 4.10.3  of the 1647-2011 document seems to describe exactly this.
Can somebody confirm that?

Thanks,
Yuri.




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Yuri Tsoglin | e Language team, Specman RnD

P: 972.3.9004305 M: 972.54.6468177 F: 972.3.9004001 www.cadence.com<http://www.cadence.com>







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Received on Wed Jun 25 07:37:46 2014

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