Date: Wed Jun 25 2014 - 07:22:10 PDT
Hi, Mantis issue #3386 is suggesting the following: Consider adding wildcard equiality operators ==? and !=? like in SystemVerilog, where x and z values act as wildcard. However, it seems that it's already in the standard. Section 4.10.3 of the 1647-2011 document seems to describe exactly this. Can somebody confirm that? Thanks, Yuri. [cid:image002.jpg@01CF9099.FF5C5170] Yuri Tsoglin | e Language team, Specman RnD P: 972.3.9004305 M: 972.54.6468177 F: 972.3.9004001 www.cadence.com<http://www.cadence.com> -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
