Attendees:

  • 11111 Himyanshu Anand
  • 01110 Kenneth Bakalar
  • 11110 Prabal Bhattacharya
  • 00001 Murtuza Bootwala
  • 01111 Eduard Cerny
  • 11100 Scott Cranston
  • 00001 Dave Cronauer
  • 11011 Mike Demler
  • 00000 Surrendra Dudani
  • 11100 John Havlicek
  • 11101 Kevin Jones (RGG Leader)
  • 11111 Scott Little
  • 00001 Thanapoom Lertpanyavit
  • 10101 David Sharrit

Decisions:


  1. The language will be an extension of SVA
  2. Will focus primarily on time domain properties

Action Items:


  1. Update Twiki and include template of time when the document was last modified to help readers figure out new content in the sections. [Himyanshu Anand]

Details:


KJ: Meeting for the last few weeks. I think we have made significant progress. There is a working draft on eda.org Twiki Requirements Gathering Group. A number of people have added content to the Twiki (Scott Little, Himyanshu Anand, Mike Demler, Ken Bakalar, Scott Cranston). We are really targeting a set of assertions AMS verification engineers. The resultant assertions are intended to be extensions of System Verilog Assertions, and fit in with System Verilog. The general consensus is time domain assertion language with dense time assertions. Introducing properties over a denser time domain.

KJ: Most of the work is defining the scope, the stronger one of the requirements was extension of System Verilog.

HA: Please send back us the feedback via email at verilog-ams@edaNOSPAM.org. Mike has added content over the weekend or yesterday.

SL: Requirements will be there in the scope. Nice to have would be beneficial to the language. Low interest is the final category which might be interesting in the future.

SL: Kevin gave a very good summary of the RGG work, so nothing much to add there.

HA: Mike since you added new content do you want to go ahead?

MD: My original taxonomy was to take as broad a view as possible and narrow it down over the time. We are mostly looking mostly at time domain. There is also a section that Himyanshu started on Analog assertions and added to that, that I would call Analog property checkers. We need to have a frame of reference going forward.

DS: Focus probably needs to stay on time domain mixed signal properties. Functionality that is truly derivable from time domain signals.

KJ: Decided SVA, time domain, AMS verification engineers. Does that fit what the larger group was thinking.

Top: The scope is ok. That is the direction that I am seeing Intel go towards. We added Mixed Signal validation and go towards digital validation again due to performance again.

HA: Anything in particular to include/exclude from the language.

Top: I am happy with where the group is going.

DC: In agreement with you now.

KJ: What is the worry I about is that there are not too many analog designers. We are running the danger that this might be limiting the scope and the audience. HA: Top can you talk to analog designers/tool developers from the Intel side and give us feedback that will help us?

Top: Yes, I can do that.

SL: It might be a pretty big jump from where we are in SVA right now to directly to Analog properties. So, it might be that we first take a half step and then go to fully analog designers.

MD: What do you see as difference between AMS and Analog properties. I sort of think they are the same.

SL: For an analog only language there are features in frequency domain, or more complex features. The thought has been that MS engines work today is Analog engines communicate analog events to digital engine. But, if we want to purely work in the Analog engine, then assertions will probably work differently.

MD: Do you think it is covered in the scope/taxonomy?

SL: Pretty much covers most of the things. But, we need just think a little bit more about them. Some of the properties that are excluded are because of the language restrictions.

-- AnandHimyanshu - 25 Feb 2009

Topic revision: r1 - 2009-02-25 - 21:00:37 - AnandHimyanshu
 
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