TWiki> VerilogAMS Web>AmsExamples>AmsExamplesADCM (2012-09-14, DavidMiller)EditAttach

Analog/Digital Converters and Modulators (ADCM)

Type Description Source
Ideal DAC Ideal digital/analog converter with variable converter size ideal_dac.va
Ideal ADC Ideal analog/digital converter with variable converter size ideal_adc.va
First Order Sigma-Delta First order sigma-delta converter firstorder_sigmadelta.va
Sample and Hold Sample and hold model
Sampler model show the application of the sample and hold model with the clock generator 		sample_hold.va
sampler.va
QAM Quadrature amplitude modulator qam16.va

Ideal Digital/Analog Converter

Module Name ideal_dac
Terminals in: input vector with digital code : input [0:dac_size-1] voltage
out: analog output terminal : output voltage
Parameter dac_size: size of converter = 8 from (1:inf)
vth: threshold voltage for input code
trise: rising time at output = 0
tfall: falling time at output = 0

Ideal Analog/Digital Converter

Module Name ideal_adc
Terminals in: analog input terminal : input voltage
clk: clock terminal : input voltage
out: output vector for digital code : output [0:adc_size-1] voltage
Parameter adc_size: size of converter = 8 from [1:inf)
fullscale: range of the analog input : 1.0
delay: delay time until output starts changing after rising clock : 0
trise: rising time at output = 10n
tfall: falling time at output = 10n
clk_vth: threshold voltage for input code
out_high: output high voltage = 1
out_low: output low voltage = 0

First Order Sigma-Delta Converter

Module Name firstorder_sigmadelta
Terminals in : analog input terminal : input voltage
clk : clock terminal : input voltage
out : output terminal : output voltage
Parameter quantizer_vth: threshold voltage for internal quantizer = 0
clk_vth: threshold voltage for clock input = 2.5
d2a_gain: gain of the internal digital/analog converter = 5

Sample and Hold

Module Name sample_hold
Terminals in: input terminal : input voltage
clk: clock terminal : input voltage
out: output terminal : output voltage
Parameter slewrate: slew rate at the output : 1ns
clk_vth: threshold voltage for clock input = 2.5

Quadrature Amplitude Modulator

Module Name qam16
Terminals in: input terminal : input [0:3] voltage
out: output terminal : output voltage
Parameter freq: modulation frequency = 1.0
ampl: output amplitude = 1.0
thresh: input threshold voltage = 2.5
tdelay: delay time = 0
ttransit: transition time = 1/freq

-- DavidMiller - 2011-03-01

Attachments Attachments
I Attachment Action Size Date Who Comment
Unknown file formatva firstorder_sigmadelta.va manage 1.1 K 2012-09-14 - 15:53 DavidMiller First order sigma-delta converter
Unknown file formatva ideal_adc.va manage 1.4 K 2012-09-14 - 15:53 DavidMiller Ideal analog/digital converter with variable converter size
Unknown file formatva ideal_dac.va manage 1.0 K 2012-09-14 - 15:54 DavidMiller Ideal digital/analog converter with variable converter size
Unknown file formatva qam16.va manage 1.0 K 2012-09-14 - 15:54 DavidMiller Quadrature amplitude modulator
Unknown file formatva sample_hold.va manage 1.2 K 2012-09-14 - 15:54 DavidMiller Sample and hold model
Unknown file formatva sampler.va manage 1.1 K 2012-09-14 - 15:54 DavidMiller Sampler model show the application of the sample and hold model with the clock generator
Edit | Attach | Print version | History: r3 < r2 < r1 | Backlinks | Raw View | Raw edit | More topic actions
Topic revision: r3 - 2012-09-14 - 15:54:54 - DavidMiller
 
Copyright © 2008-2025 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki? Send feedback