Time: 16.00:00 UTC (9:00 PDT)

Duration: 1 hour

Agenda

• Reminder of IEEE patent policy
  See: http://standards.ieee.org/board/pat/pat-slideset.ppt
• Minutes approval
• Email ballot results
• Mantis items in progress
• Opens

Attendance Record

Legend:

x = attended

- = missed

r = represented

. = not yet a member

v = valid voter (2 out of last 3 or 3/4 overall)

n = not a valid voter

t = chair eligible to vote only to make or break a tie

Attendance re-initialized on 2016-03-09:

v[.x-xxxxx---xx-] Mehbub Ali (Intel)

n[.xx--x------x-] Ang Boon Chong (Intel)

n[x-x-xx-x-x—x-] Shalom Bresticker (Accellera)

n[.x------------] Dennis Brophy (Mentor Graphics)

v[xxxxxxxxxxxxxx] Eduard Cerny (Synopsys)

v[xx-xx-xxxxxxxx] Ben Cohen (Accellera)

t[x-xxxxxx-xxxxx] Dmitry Korchemny (Synopsys - Chair)

n[xxx-x-x-------] Manisha Kulshrestha (Mentor Graphics)

v[xxxxxxxx-xx-xx] Anupam Prabhakar (Mentor Graphics)

v[xxxxxxxxxxxx-x] Erik Seligman (Intel – Co-chair)

n[x-x-xxxx-xx-x-] Samik Sengupta (Synopsys)

|- attendance on 2016-09-21

|--- voting eligibility on 2016-09-21

Minutes

IEEE patent policy reminder

Minutes approval

Erik: Move to approve the minutes from 21-Sep-2016.

Ben: Second.

Motion passed: 4y/0n/0a.

Email ballot results

Issue 2555 passed.

Issue 3614 failed.

Ben: 3614 Need to be consistent and use logical operators instead of bitwise.

Erik: There are several comments about the language.

Anupam: Will implement the comments and submit the updated proposal (done).

Erik: Move to accept the updated proposal 3614.

Ed: Second.

Motion passed: 4y/0n/0a.

Mantis items in progress

2842: Randomization of free variables in deferred assertions

Anupam: Let’s postpone to the next PAR, because the solution should be rather involved.

Erik: Dmitry to send an email reminder about proposal submission deadline.

Opens

Ben: Need to introduce syntax for local variable declaration immediately inside assertion.

Erik: This is an enhancement, and we are not authorized to address it in this PAR.

Ben: Need to standardize interoperability between SV and VHDL.