P1076 Web>VHDL202xCollectedRequirements (2020-04-28, PeterLadow)EditAttach

Proposal Summary + Link to Proposals

Status Values:

RAW - Initial development, may change frequencly, comments welcome
RFC - Draft, needs comments
REVIEW - Requesting more formal review in working group meeting
STABLE - Done
LCS - LCS Editing, Volting, Approval, or Rejection in process

Item	Who	Status	LCS Link	Description
File IO / Textio Updates		RAW	LCS2016_006a
File IO / Directory IO			LCS2016_006c
Sequential Declaration Regions (corresponding short form)			LCS2016_007 LCS2016_007a
Date/TIme Functions			LCS2016_011
Attributes for Enumerated Types
New Attributes
'designated_type
Indexing Constrains from Initial Values for Signals and Variables
LongIntegers
Selected names for types (implementation of external names for types)
Garbage Collection
Protected Types with Generic Clause
Allow for conditional expressions in a declaration (baseline)
Record Introspection Type Reflection
Interface - defines new mode view construct for composite interfac objects
Interface - `CONVERSE for a mode view
Protected Type: Shared Variables on Entity Interface
Map Generics on Subprogram Call
Array Type Generics
Allow odering on any scalar array - related to Array Type Generics
Bidirectional Connections
Function Knows Return Vector Size
Closes related record types
All Interface Lists Can Be Ordered
Conditional Return Statement
Extended Ranges
Updating IEEE Standard References
Repair example in Section 5.6.3
Precedence of Unary Operators
Repair Example in Section 23.21
DREAD, DWRITE, Integer D, H, O B Read and Write
Allow access to system environment variables
Deferred Shared Variables
Deferred Shared Variables
Extenstion to LCS 099 - intended to make things more locally static
Generate Statement Alternate Path Names - beware of pathname for external names vs RV'path_name
Generate Statement Alternate Path Names - Dissentiing Opinion
'access attribute
Long Integers - 512 bit
Long Integers - 64 bit integer and subtypes
Long Integers - 64 bit integer and 32 bit integer
Anonymous types for external names (implementation of external names for types)
Interface - defines new null mode for composite interface element actual/formal isolation
Additional Operators to Integers
Wait Level - Signal Expressions in Signal Parameter Map
Bidirectional Connections
Extra comma at the end of lists
Fix 2008 Context Clause
The sensitivity list for process(all) should not include signals in all reachable subprograms
Protected Types with Public Signals
Package as an Interface Construct
Implicit Parameter and Port connectinos
Bidirectional Connections
Closely related record types
Record Introspection
Record Introspection and Indexing
Process-All and Implicit Signals
Package Name Case Sensitivity
Integers of arbitrary length
Long Integers 64 bit type
Modular Integer Types
Additional Operators for Integers - Logic
Implicit Conversions for Like Types
Extended Integers
Physical Type Range
Enhanced Integers
Modify Report Statement to return calling path of subprograms
DPI Proposal
Hierarchical Libraries
External names for types
Configuration Spec for Direct Instances
Attributes for PSL
Protected Types with Wait and Private Signals
API for Assert
Slicing Multidimensional Arrays
External Non-Shared Variable Name
New Predefined Attributes: actual and formal
Abstract Packages
Wait with Level Check
Unions and/or Variant Records
Expressions in Bit String Literals - Dynamic Sizing
Relaxed OTHERS rules in aggregates
Deferred Shared Variables
Overload Assignment Operator
Extended String Literals
Extended Ranges
Extended user-defined attributes
Access to logic representation of VHDL objects
numeric_std, fixed, and float bugs adn consistency updates
Real Matric Math Package
Flag metavalues detected by ??
Read differences of bit_vector and std_logic_vector
Updates to standard packages - split into LRM and Packages
Signatures for Association List Aspects
Assigning 2008 Entities to Attributes Classes
Repair LRM Example 14.2
Repair LRM Example 7.3.2.1
Repair Text on Context Clauses
Repair LRM Section 16.8.2.4.3 Missing Paragraph Text
Repair example in LRM section 5.6.3
Bit String Literals Corner Cases
Repair Generate Statements
Force and Out Port
String Representation for extended identifiers
Alternate Label in Path Nume Bug 293
Repair Example in Sectdion 23.21
Typographical Issues in IEEE Std 1076-2008
Process-All should not be sensitive to signals in packages
VHPI Impact
VHPI for PSL
define parameters for env.stop
Standard instances of float
Vector literal introspection
Object orientation
Wait with repeat count
Cross Language Instances
std_ulogic, resolved, and '-'
Create natural_vector
Architecture generic
Multiple top-level designs
Preponed processes (clocks)
Update std_logic_arith
Dynamic process, instances, fork/join
Shorthand subprogram declarations
Sequential signal declarations
Truth tables
Asynchronous channels
Clocked shorthand
Dynamic rewiriing
Composing path to external names
Attribute shorthand
Support synthesis of reals
Named package bodies
Unique condition - Orlf
Synthesizable reports and assertions
Multicycle path specification
2 and 4 state values
Specify timign constraints
Synthesizable 'event attribute
Object inspection
Use of unicode
Move definition of TEXT, INPUT, OUTPUT
Stop Binary/Octal/Hex Read At trailing underscore
VHDL AMS 1076.1 Proposals
Table Driven Modeling
Vector/Matrix Package

Peter LaDow - 2020-04-28

Comments

Topic revision: r1 - 2020-04-28 - 22:26:31 - PeterLadow

P1076

Proposal Summary + Link to Proposals

Item

Who

Status

LCS Link

Description

VHDL AMS 1076.1 Proposals

Comments