interface_declaration ::=
interface identifier of composite_subtype_name is
interface_declarative_part
end interface [ interface_simple_name ] ;
Apart from port configurations, the interface could contain various decalarations pertaining to the Interface. At first I thought that the interface should not infer any form of hardware, mainly being used to provide simplified connectivity and functions/procedures used for abstract test monitoring /stimulus of protocols and transactions. However, maybe within the object entity (as opposed to the structural interconnect side) it could be used to generate the interface I/O functions.port_configuration_declaration ::=
port configuration identifier is
[ formal_generic_clause ]
formal_composite_port_clause
end port configuration [ port_confguration_simple_name] ;
composite_port_clause ::=
port ( composite_port_list ) ;
composite_port_list ::= composite_interface_list
composite_interface_list ::=
composite_interface_element { ; composite_interface_element }
composite_interface_element ::= composite_interface_declaration
composite_interface_declaration ::=
element_identifier_list : composite_mode_declaration ;
composite_mode_declaration ::=
mode [ := static_expression ]
mode ::= in | out | inout | buffer | linkage | composite_mode | null | custom_mode
composite_mode ::=
composite ( composite_mode_clause )
composite_mode_clause ::= composite_interface_declaration
custom_mode ::= mode'port_configured_composite_mode
port_configured_composite_mode::=
port_configuration_simple_name [ ( generic_association_list ) ]
package CPU_BUS_pkg is -- address & data subtypes subtype ADDR_vst is Std_Logic_Vector(15 downto 0); subtype DATA_vst is Std_Logic_Vector(15 downto 0); -- slave array definitions constant SLAVE_MAX_jc : Positive := 8; subtype SEL_jst is Natural range SLAVE_MAX_jc-1 downto 0; subtype SEL_vst is Std_Logic_Vector(SEL_jst); -- the interface sub-records and arrays type MASTER_r is -- Master record record ADDR_vl : ADDR_vst; -- Address bus to slave devices DATA_vl : DATA_vst; -- Data bus from master to slave WE_l : Std_Logic; -- Write enable from master SEL_v : SEL_vst; -- Slave enables from master end record MASTER_r; type SLAVE_r is -- Slave record record DATA_vl : DATA_vst; -- Data bus from slave to master ACK_l : Std_Logic; -- Acknowledge to master end record SLAVE_r; type SLAVE_at is array(SLAVE_IF_SEL_jst) of SLAVE_r; -- Array of slave return records -- the main interface record type CPU_BUS_r is -- Bus interface record record MASTER_rl : MASTER_r; -- Master record to slaves SLAVE_al : SLAVE_at; -- Array of slave records to master end record CPU_BUS_r; -- the interface declaration interface CPU_BUS_if of CPU_BUS_r is -- these configurations define custom modes which can be -- used on a port mapping of a 'CPU_BUS_r' record type -- for a master mapping: -- the master element (a record) is an output -- the slave element (an array) is an input port configuration MASTER_pcfg is port( MASTER_rl : buffer; SLAVE_al : in ); end port configuration MASTER_pcfg; -- for a slave mapping: -- the master element (a record) is an input -- the slave element (an array) is a composite mode -- the generic selects the array element to drive as an output -- the other array elements are set to null mode (not driven or read) port configuration SLAVE_pcfg is generic( SEL_jg : SEL_jst ); port( MASTER_rl : in; SLAVE_al : composite( SEL_jg : buffer; others : null ) ); end port configuration SLAVE_pcfg; end package CPU_BUS_pkg;
use work.CPU_BUS_pkg.all entity MASTER is port( CLK_i : in Std_Logic; CPU_BUS_cp : mode'CPU_BUS_if.MASTER_pcfg CPU_BUS_r; -- Master port to slaves RST_i : in Std_Logic ); end entity MASTER;
use work.CPU_BUS_pkg.all entity SLAVE is generic( SLAVE_SEL_jg : SEL_jst ); port( CLK_i : in Std_Logic; CPU_BUS_cp : mode'CPU_BUS_if.SLAVE_pcfg( SEL_jg => SLAVE_SEL_jg ) CPU_BUS_r; RST_i : in Std_Logic ); end entity SLAVE;
signal CLK_s, RST_s : Std_Logic; signal CPU_BUS_rs : CPU_BUS_r; begin MASTER_i0 : MASTER port map ( CLK_i => CLK_s, CPU_BUS_cp => CPU_BUS_rs, RST_i => RST_s ); SLAVE_i2 : SLAVE generic map ( SLAVE_SEL_jg => 2 -- slave instance 2 ) port map ( CLK_i => CLK_i, CPU_BUS_cp => CPU_BUS_cs, -- is mapped through to CPU_BUS_cs.SLAVE_al(2) RST_i => RST_i ); SLAVE_i4 : SLAVE generic map ( SLAVE_SEL_jg => 4 -- slave instance 4 ) port map ( CLK_i => CLK_i, CPU_BUS_cp => CPU_BUS_cs, -- is mapped through to CPU_BUS_cs.SLAVE_al(4) RST_i => RST_i );