Accellera VHDL-TC Extensions-SC

Interfaces

Jim Lewis, SynthWorks

jim@synthworksNOSPAM.com

Version 0.1 Draft, 12 Jan 2006

Abstract

This paper covers the requirements for interfaces in VHDL, potential use models, and alternatives to implementing them.

Revision History

Version 0.1 12-Jan-2006, Jim Lewis. Initial work in progress draft.

1. Preface

This document is a work in progress. Some of the terminology in this area seems to be inconsistent and evolving, so I appologize in advance if I use a term in a way that is either different from what you have seen or just plain wrong.

Topic revision: r1 - 2015-08-03 - 17:05:27 - BrentHahoe
 
Copyright © 2008-2024 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki? Send feedback