Reflection

Proposal Details

Current Situation

Generically converting types from one kind to another currently isn't possible in VHDL. This causes a lot of code duplication, or people resort to code generation. Reflection offers a mechanism to inspect & modify any VHDL type or value.

Requirement

Enable conversion (implicit or otherwise) between records and vectors (single dimensional array) and therefore unions between two records (or a record and a vector).

• To facilitate this, provide a language/syntax/synthesisable (and also useful for testbenches) mechanism for:
  • iterating over the elements of a record in a deterministic order.
  • assigning the value of a record element where the name of the element is stored in a variable.
  • determining the type of an element (record, scalar, vector, enumeration).
  • reaching the type of an object from an instance.

Enable modification of values

• see randomize example

Enable passing generic values (replace anonymous types proposal)

Implementation details

see LCS-2016-041

Use Cases

Related Issues:

Code Examples

moved

Arguments FOR

Arguments AGAINST

Probably only works for simulation & elaboration. It's probably too much abstraction for synthesis tools. I believe the other proposals have the same issue.

General Comments

Supporters

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