P1076 May 26, 2011 Meeting Minutes

Attendees:

JohnShields, JimLewis, MartinThompson, DavidBishop, ChrisHiggs, JarekKaczynski, PeterFlake, HansTiggeler

Agenda:

Approve April 28 meeting minutes: Motion: JohnShields 2nd: JarekKaczynski

Review VASG Working Group Operating Procedures

Continue discussion of language change requirements.

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Harry Foster Presentation on Survey (John Shields)

  • Purpose (John Shields)
    • Where are languages heading. Should we focus on integration of other languages?
    • Should we bring verification to VHDL?
  • Hans: Interested in direction of PSL. Not interested in how wonderful SV is.
    • Peter Flake, Martin: Also interested in direction of PSL.
  • Peter: Are assertions making it into FPGA design houses?
  • Hans: Sees usage of PSL for functional coverage (PSL also more capable for formal)
  • Survey Questions for Harry
  • Jim: What was the selection criteria for the survey? Who was selected? Who responded?
  • Jim: Statistics for just FPGA?
  • Jim: Relative number for commercial vs. Mil/Aero?
  • Jim: Within FPGA, relative number of commercial vs Mil/Aero?
  • Jim: What are the verification statistics for Americas and Europe separately?
  • Jim: The statistics seem to show that ASIA numbers are much bigger than India, Europe and America, India. Relative to ASIA, how big is Europe, Americas and India?
  • Action Item (All): Post questions for Harry for him to answer in the presentation on the Mentor verification survey. This will allow him to be prepared. It wastes time if he needs to research answers after the meeting.

Matrix Packages (David Bishop)

  • New package with matrix multiplies for signed, unsigned, fixed, ufixed - will post. Can we do type generics?
  • Issues with having different implementations.
    • Jim: Named package bodies that are selectable?
      • Named package bodies are also convenient for memory model packages that are based on protected types where the package declaration defines the interface and different bodies reflect different implementations (such as sparce implementations for fast simulation vs. highly accurate VITAL memory model).
      • Named package bodies would also potentially allow having a set of procedures that implement registers with reset - and on a design by design basis, they can be selected to be either synchronous or asynchronous reset.

How do we move items forward?

  • In the previous revision, we brainstormed and then worked on items. When the work was transitioned to Accellera, we handed off a list and proposals in various states of completion.
  • For this revision, how do we rank items and move them forward without having a complete list?
    • Some things seem easy as they have significant interest: DPI, RTL Building Block
  • Action Item (All): Take ownership of items that interest you and update the collected requirements list

Action Items:

  • All: Review VASG Working Group Operating Procedures
    • Discuss on reflector. Vote after next meeting.
  • All: Officer elections soon. We need chair, vice-chair, and secretary.
    • All of these are non-technical administrator type roles
  • All: Please fill in your TWIKI information. The IEEE standard working group operating procedures require the collection of information about working group members and submitting it to IEEE (see the VASG Working Group Operating Procedures above).
  • All: Post questions for Harry for him to answer in the presentation on the Mentor verification survey. This will allow him to be prepared. It wastes time if he needs to research answers after the meeting.
  • All: Take ownership of items that interest you and update the collected requirements list

Next Meeting Date (proposed):

Thursday June 30 at 8 am

Topic revision: r5 - 2020-02-17 - 15:36:21 - JimLewis
 
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