P1076 January 5, 2012 Meeting Minutes

Attendees:

Agenda:

  • New items from Collected requirements list
    • Registers and clocks
    • Implicit Parameter and port connections
    • New issue from John Shields on Out ports and forcing
  • Approve meeting minutes from December 15: Motion: Jarek, Second: Peter

Implicit Parameter and Port Connections

  • Reviewed Collected requirements item
  • Peter: Likes proposal part 2 better than part 1. In particular having the "=> others" notifies readers that there are other parameters.
  • What should happen if "=> others" is used and nothing is there?
    • Other language allow it silently, however, this is more of an error/warning type of thing here
  • Which is easier for vendors?

Clocked Shorthand

  • requirement: transformation between async, sync, and power-on reset
    • maybe power-on and choice of async and sync as power-on process is to slow for some systems
  • Syntax 2: kind of like verilog.
  • If can pass functions, then could at top level pass rising_edge or falling_edge to change polarity of clock.
  • Syntax 3:
    • Nice to generalize the iteration count and bring it into wait also - use PSL notation?
    • Q <= D @ 2 ; would still produce an output every clock - like transport delay
    • Need to review the behavioral SystemC methods to account for higher level stuff
    • Look at BlueSpec?
  • Could also be done with a package of subprograms
  • Driving need/Priority: Not very high

Out Ports and Forcing

  • What would we do for the next revision?
  • Peter thinks interpretation A is a reasonable interpretation. Martin and Jim concur.
  • David believes that the intent of VHDL-2008 was to make out and buffer identical. Jim concurs.
  • What does a designer need it to do? What are the use models/methodology?

Next Meeting Date:

Thursday January 26, 8 am Pacific

Topic revision: r5 - 2020-02-17 - 15:36:20 - JimLewis
 
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