P1076 August 11, 2011 Meeting Minutes

Attendees:

By signing in, I also indicate that I have reviewed the IEEE patent policy and have made any required disclosures.

Agenda:

Simulation Controls

  • ?Merge with DPI?
  • Add standardized environment variables: IE: language revision, tool type (sim vs. synthesis)
  • AI: David Koontz - start initial proposal on simulation controls

Encryption

  • AI: Jarek K. start proposal on encryption - with input from John S.

DPI

  • AI: Peter Flake - start proposalon DPI

Implicit Port & Parameter Connections

  • Cross language port associations
  • VHDL to VHDL associations
  • AI: Jim Lewis - start proposal on Implicit Port & Parameter connections

Configuration Declarations & Direct Entity Instantiations

  • Configuring direct entity instantiations (architecture, generics, and ?ports?)
  • No Owner

Synthesizable Constructs

  • RTL Macros ?!??
    • AI: Daniel - please delete your separate comment on rtl macros and add your support to the appropriate spot on the collected requirements page.
  • Synthesizable Generics
    • AI: Daniel: Request for synthesizable generics needs more information. You seem to be talking about an implementation that solves some sort of problem. Please restate what you want in terms of the problem you are trying to solve (such as dynamically reconfiguarable hardware, ...). This way we can help you think about how to solve the problem. Your observation that generics are static is true - that is what generics are. Your observation that ports are dynamic (change during run time) is also true.
  • Dual-edge coding styles
    • 1076.6-2004 has coding styles for dual-edge, but not the one specified. they require rising_edge and falling_edge specifications. Some synthesis tools are supporting styles like this for dual-clocked memories.
    • AI: Daniel: Do an internet search on 1076.6-2004 coding styles for multi-clock flip-flops and indicate whether these indicate meet your needs (you might start on Jim's webpage).
  • Synthesis of reals?
    • Fixed vs. Float? How to size the number?
    • Is there a way to simulate with real and then use fixed/float in the actual design?
    • AI: Daniel: Do the VHDL-2008 fixed and floating point packages satisify your need for synthesis of reals?

Synthesizable assertions

  • zeroonehot
  • AI: Daniel please elaborate on your requirement for synthesizable assertions
  • No owner

Conditional Compilation

  • Help with language transition (VHDL-2002 vs VHDL-2008 and packages to include)
  • Help with different design variations (ie: number of ports)
  • AI: John Shields - ?pre-processor style? conditional compilation

Officer Elections

  • AI: John Shields - start call for nominations for officer elections

Action Items:

  • AI: David Koontz - start initial proposal on simulation controls
  • AI: Jarek K. start proposal on encryption - with input from John S.
  • AI: Peter Flake - start proposalon DPI
  • AI: Jim Lewis - start proposal on Implicit Port & Parameter connections
  • AI: John Shields - ?pre-processor style? conditional compilation
  • AI: John Shields - start call for nominations for officer elections
  • AI: Daniel Kho
    • AI: Daniel - please delete your separate comment on rtl macros and add your support to the appropriate spot on the collected requirements page.
    • AI: Daniel: Request for synthesizable generics needs more information. You seem to be talking about an implementation that solves some sort of problem. Please restate what you want in terms of the problem you are trying to solve (such as dynamically reconfiguarable hardware, ...). This way we can help you think about how to solve the problem. Your observation that generics are static is true - that is what generics are. Your observation that ports are dynamic (change during run time) is also true.
    • AI: Daniel: Do the 1076.6-2004 coding styles for multi-clock flip-flops (see slide 13) meet your needs for dual clock synthesis. Not shown is a coding style with separate if - end if; I note that some FPGA vendors are starting to support similar coding styles for dual-clock memories.
    • AI: Daniel: Do the VHDL-2008 fixed and floating point packages satisify your need for synthesis of reals? If not, please clarify the intent of your proposal (simulation speed?), so that alternatives can be traded off (such as making type real synthesizable vs. using type generics and swapping in type real for simulation and a fixed or floating point type for synthesis).
    • AI: Daniel: in simplify port mapping - current language allows leaving off ports that are open (when it is legal for them to be open). Does this meet your needs? Alternately do you require an others for some reason? If so, please explain. One thing the current language does not allow is array ports that are partially open - some bits mapped and some bits open.
    • AI: Daniel more expressive generate statements - a variation of what you proposed is already part of VHDL-2008. Please research and update your comments accordingly.

Next Meeting Date (proposed):

Thursday August 25, 8 am Pacific

Topic revision: r4 - 2020-02-17 - 15:36:20 - JimLewis
 
Copyright © 2008-2020 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki? Send feedback