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LRM 7.3.2.1 page 100 near bottom
entity AND_GATE is generic (I1toO, I2toO: DELAY_LENGTH := 4 ns); port (I1, I2: in BIT := '1'; O: out BIT); end entity AND_GATE;
LRM 7.3.2.1 page 100 near bottom
component AND_GATE is generic(I1toO, I2toO: DELAY_LENGTH := 4 ns); port (I1, I2: in BIT := '1'; O: out BIT); end component AND_GATE;
Comments
Hopefully it will save someone else time to know that the initial value is needed because it is left open in the configuration of L2 in the declarative region of Half_Adder.Structure.
-- Ryan Hinton - 2016-12-19