P1076 Web>VHDL2017>LCS2016_055a>LCS2016_055a_History (2017-07-19, JimLewis)EditAttach

Language Change Specification for Syntax regularization for endings

Proposal

LCS Number:	LCS-2016-055a History
Version:	1
Date:	05-March-2017
Status:	Voting
Author:	Ryan Hinton Jim Lewis
Email:	Main.RyanHinton Main.JimLewis
Source Doc:	Syntax regularization - end
Summary:	Make syntax for component declatations more similar to entity statements
Derivative of 055	LCS_2016_055

Voting Results: Cast your votes here

Yes:

No:

Abstain:

Brent Hayhoe - 2017-03-06 - ver 1 Comment below

Comments

As has been stated by many others, optional keywords after the 'end' keyword is historically a bad decision IMHO. However, optional simple names makes sense.

I do not like this as a concept but will not block it, hence my abstention.

(Ditto for optional 'is' keyword as well.)

-- Brent Hayhoe - 2017-03-06

@Brent: Thanks for not blocking. Your concerns are shared by many others. This is why this condensed LCS only addresses the discrepancy between the obviously closely related declarations of entities and components.

-- Thomas Preusser - 2017-03-06

Topic revision: r1 - 2017-07-19 - 10:05:42 - JimLewis

P1076