Repair LRM Example 7.3.2.1

Proposal Details

• Who Updates: DanielKho
• Date Proposed:
• Date Last Updated:
• Priority:
• Complexity:
• Focus:

LCS

LCS-2016-I06

Current Situation

The following example is taken from Section 7.3.2.1 of the LRM.

entity and_gate is
    generic(i1_o, i2_o: delay_length := 4 ns);
    port(i1, i2: in bit; o: out bit);
 end entity and_gate;
...

for L2: and_gate use entity work.and_gate(behavior)
        generic map(3 ns, 4 ns)
        port map(i1=>i1, i2=>open, o=>o);

configuration different of half_adder is
 ...
        for L2: and_gate
            generic map(2.8 ns, 3.25 ns)
            port map(i2=>Tied_High);
        end for;
    end for;
end configuration different;

This example tries to incrementally bind an open input port (i2), yet the port does not have a default value.

Section 6.5.6.3 states:
"It is an error if a port of mode in is unconnected (see 6.5.6.3) or unassociated (see 6.5.7.3) unless its declaration includes a default expression (see 6.5.2)."

This renders the example invalid, as the port i2 in the configuration specification L2 is of mode in and is left unconnected, yet it does not have a default value.

Requirement

We propose to specify a default value to the i2 port, so as to make this example valid:

entity and_gate is
    generic(i1_o, i2_o: delay_length := 4 ns);
    port(i1, i2: in bit := '1'; o: out bit);
end entity and_gate;

Implementation details

Code Examples

Use Cases

Arguments FOR

Daniel, interesting that in your reflector Email you had the default value set to '0' and have changed it to 'Z'... and that I thought that it should be 'H'... neither of which are valid values for type BIT.

I think we need to change it to '1' (assuming active-high inputs) in order to enable the 'AND_GATE' by default? -- BAH - 2013-11-21

Brent, yes I agree to change it to '1' since the example uses type BIT. -- DanielKho - 2013-12-12

Arguments AGAINST

General Comments

Supporters

-- DanielKho - 2013-11-14 -- Brent Hayhoe - 2013-11-21

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