P1076 September 1, 2016 Meeting Minutes


  • Brent Hayhoe, Kevin Jennings, Peter Flake, Rob Gaddi, Jim Lewis, Patrick Lehmann, Jing Pang


Meeting Discussion

  • Partiallyconnectedvectorsonportmap - finalization hopefully
    • Agreed that partially connected vectors should be allowed. Agreed LRM change language sounds right. Should review next week in context of http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2041.txt
    • For partially mapped vectors, usage of keyword open required, even on inputs that are initialized.
    • For input initialization, first initialization value is calculated, then any elements are used if unmapped
    • Kevin suggests that we do not define how initialization is handled but instead rely on current language rules
    • See section 14.3.5 port map aspect of elaboration
    • Use model for partially connected input?
      • Use slice of an IP, but not all of it. Some IP only use some inputs under some configurations. See below.
    • Rob will research 14.3.5 regarding the rules for initialization.
    • Lieven: Do arrays still need to be mapped contiguously? Is anyone willing to write an LCS for this?
  • Interfaces - continue & review Rob's unconstrained signals modification
    • Reviewed updated with unconstrained interface for SPI bus. See SpiRevised
Use case - Hardmacro IP core on an FPGA with configurable interface width:

inst : MGT
  generic map (
    -- ...
    -- ...
  port map(
    TX_Data(31 downto 0) => TX_Data,
    TX_Data(63 downto 32) => (others => '0'),
    -- ...
    RX_Data(31 downto 0) => RX_Data,
    RX_Data(63 downto 32) => RX_Data_float, -- we can't use 'OPEN' here
    -- ...

Review and Approve Meeting Minutes and Decisions by Attendees

Rob, Brent, All

Review and Approve Meeting Minutes and Decisions by non-attendees

Agree. -- MartinZabel - 2016-10-07

Next Meeting: Wednesday September 7, 2016, 11 am Pacific

Previous Meeting: Thursday August 25, 2016

Topic revision: r6 - 2020-02-17 - 15:36:18 - JimLewis
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