P1076 October 6, 2016 Meeting Minutes

Attendees:

• Brent Hayhoe, Lieven Lemiengre, Kevin Jennings, Patrick Lehmann, Rob Gaddi, Jim Lewis, Peter Flake, Jing Pang

Agenda:

Meeting Discussion

• Interfaces - continue.
• AI: Jim talk to vendors about space ship operator and its implementation.
• AI: What ranked proposal do you want to work on.
  • If you are working on an LCS, change the name of the item to your name.
  • Change status to LCS in progress.
• By December, need LCS for proposals that will go into standard.
• December to March - prepare final document.

Reviewed Rob's AXI Interfaces implementation. See https://gitlab.com/IEEE-P1076/Interfaces/blob/axi4/AXI4.vhdl

See Patrick Lehmann's post about getting a GitLab account.

Filled in the details of the map function

    map axil_addr_remap(
        bundle mst : b_axil_mst t_axil;
        constant slv_addr_width : positive
    ) to b_axil_slv is
    begin
        -- These are elaboration time assertions, not run time.
        assert slv.wa'length <= mst_addr_width
            report "Slave address wider than master.";
        assert slv.wa'length == slv.ra'length
            report "Slave read/write addresses do not match.";
        
        map (
          wa => map (
             addr => mst.wa.addr(slv_addr_width-1 downto 0),
             hs   => mst.wa.hs,
             prot => mst.wa.prot
          ),
          wd => mst.wd,
          wb => mst.wb,
          ra => map (
            addr => mst.ra.addr(slv_addr_width-1 downto 0),
            hs   => mst.ra.hs,
            prot => mst.ra.prot
          ),
          rd => mst.rd
        );
    end map function axil_addr_remap;

Worked on how to handle top level connections

entity tb_axil is
end entity tb_axil;

architecture Testbench of tb_axil is

    signal clock_and_reset : t_axi_clock := (
      clk => '0',
      resetn => '1'
   );

    signal bus_cpu  : t_axil(
            wa(addr(31 downto 0)),
            ra(addr(31 downto 0))
        );
    signal bus_mem1_r : t_axil(
            wa(addr(9 downto 0)),
            ra(addr(9 downto 0))
        );
    signal bus_mem_r : t_axil(
            wa(addr(21 downto 0)),
            ra(addr(21 downto 0))
        );

    signal gpio : std_logic_vector(15 downto 0);
   
begin

   INST_FAKE_RESET : process
   begin
      clock_and_reset.resetn <= '0', '1' after 50 ns;
      wait;
   end process;

   INST_FAKE_CLOCK : process
   begin
      clock_and_reset.clk <= not clock_and_reset.clk after 10 ns;
   end process;
   
   -- How to tackle the issue of connecting clock to the three busses
    -- Option 1: Space ship operator   
   bus_cpu.clk  <=> clock_and_reset;
   bus_mem1.clk <=> clock_and_reset;
   bus_mem2.clk <=> bus_cpu.clk;
   
   -- Equivalent forms
   bus_cpu.clk  <=> clock_and_reset2;
   clock_and_reset2 <=> bus_cpu.clk;
   
    -- Option 2:  Mapping option 1
    INST_CPU : entity work.axil_cpu
        port map (
            axi => map(
               clk => clock_and_reset
               others => bus_cpu
            ),
            gpio => gpio
        );
    
    -- Option 2:  Mapping option 2
    INST_CPU : entity work.axil_cpu
        port map (
            axi => map(
               clk => clock_and_reset
               others => bus_cpu
            ),
            gpio => gpio
            clk_and_reset => clk_and_reset
        );
            
   -- Option 3:  Do bus expansion at interface, however, defers issue to having to do space ship operator or other inside
   INST_CLK_RESET : entity work.clk_reset_blk
       generic map (NUM_AXI => 3) ;
       port map (
         A(0) => bus_cpu.clk,
         A(1) => bus_mem1.clk,
         A(2) => bus_mem2.clk
         
         clk => clk,
         rst => rst
       ) ; 
        
    INST_INTERCON : entity work.axil_interconnect
        port map (
            cpu => map( -- view is slave 
               clk => clock_and_reset
               others => bus_cpu
            ),    
            mem1 => bus_mem1,  -- view is master
            mem2 => bus_mem2
            clk_and_reset => clk_and_reset
        );
        
    INST_MEM1 : entity work.axil_mem_slave
        generic map (
            ADDR_WIDTH => 10
        ) port map (
            axi => mem1
            clk_and_reset => clk_and_reset
        );
        
    INST_MEM2 : entity work.axil_mem_slave
        generic map (
            ADDR_WIDTH => 22
        ) port map (
            axi => mem2
            clk_and_reset => clk_and_reset
        );

end architecture Testbench;

Review and Approve Meeting Minutes and Decisions by Attendees

Kevin, Rob

Review and Approve Meeting Minutes and Decisions by non-attendees

-- ThomasPreusser - 2016-10-07

Great work! I am really hoping for the spaceship. In the end, it is just another way of defining an alias. So, I do not see why it should be impossible.
A few minor comments:

• The implementation of the map function seems to lack the keyword function in its header.
• The result of the function is computed by a map statement. What differentiates this type of statement from a return? The latter appears to be the more natural choice for a function.
• In a port declaration of an entity: Why must bundles be annotated with the keyword bundle when they have a bundle mode anyways? Maybe, this should be an optional feature, which goes along with optionally annotating classic ports as signals?

-- MartinZabel - 2016-10-07

Just a comment: I think, on INST_INTERCON it should be only cpu > bus_cpu because =clk_and_reset is provided through another port.

-- PatrickLehmann - 2016-10-12

A "map function" is no function, because a (normal) function implies a unidirectional assignment. For now, "map function" is a working title. Because the "map function" is no function, return statements cann't be used to compute the result of a mapping operations, which is bidirectional. A bundle itself is no mode like in, out or inout. It was discussed, but does not apply to the current ideas for a solution.

Next Meeting: Thursday October 13, 2016, 11 am Pacific

Previous Meeting: Thursday September 29, 2016