P1076 November 3, 2016 Meeting Minutes


  • Kevin Jennings, Jim Lewis, Jing Pang, Peter Flake, Rob Gaddi, Brent Hayhoe, Lieven Lemiengre


Meeting Discussion

  • Conditional Compilation
    • Peter wrote an initial proposal
    • Logic operations and Equality, inequality
    • Vendor = name vs. vendor_name defined?
    • Use strings. Checking for an unset variable is vendor = ""
    • Need to define a set of variables that vendors are to use:
      • ToolType {"synthesis", "simulator", "equivalencechecker", "formal"}
      • ToolName match vendor case
      • VendorName
      • ToolVersion
      • VHDLVersion
      • OptimizationLevel - low level optimization is equivalent to debug mode
      • language predefined strings should be defined to be either all lower case or all upper case
      • String comparisons will be case sensitive, just like the language
    • What does Verilog do? Perhaps we should copy that or do a subset?
      • Peter not willing to work on a Verilog-like one.
      • Includes macros and include files but not boolean operators
      • Concluded that Verilog one is more complicated than we want
  • Rob LCS on Optional semicolons. Also includes optional commas.
  • Voting on LCS
    • In LCS add vote section
    • Voting:
      • vote: Yes, No, Abstain
      • record date of the vote
      • record version number/date of LCS (from top of LCS)
    • With no votes, it is helpful to provide a rationale. Is it the whole LCS or just parts?
    • Split controversial pieces out as separate LCS.
    • Issues: Record issues in comments section
    • Vote now while in flux or wait until it is done?
    • If major updates, then notify people it has changed.

Review and Approve Meeting Minutes and Decisions by Attendees

Rob, Brent, All

Review and Approve Meeting Minutes and Decisions by non-attendees

Approved -- PatrickLehmann - 2016-11-04

Next Meeting: Thursday November 10, 2016, 11 am Pacific

Previous Meeting: Thursday October 27, 2016

Topic revision: r4 - 2020-02-17 - 15:36:17 - JimLewis
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