P1076 May 26, 2016 Meeting Minutes

Attendees:

• Brent Hayhoe, Lieven Lemiengre, Patrick Lehmann, Jim Lewis, Peter Flake, Jing Pang, Kevin Jennings

Agenda:

Meeting Discussion

• Review PrivateDocuments file: _summary_vhdl_requirements_priority.xlsx
• Restart at line 75. Next meeting restart at 86
• 75: Std_ulogic and resolution of '-'
  • Resolved to create a separate resolution function
  • Could consider it a bug fix. Unlikely someone would be impacted by the change.
• 76: Closely related record types
  • Currently requires an explicit conversion function.
  • Could be handled by mapping operations being created for interface
  • If pick option 3: name and position can keep it safest.
  • How often does this happen? Will it increase when we add interfaces.
  • Revisit after interface implementation with Ryan
• 77: Unique Condition - OrIF
  • When decode logic is local, current opinion and observations is that synthesis tools will currently see the logic is mutual exclusive and reduce the logic to the desired solution.
  • Table this one.
• 78: Synthesizable Reports and Asserts
  • Needs more refinement to be actionable.
  • Is it include report/assert into gate level netlist or is translate report/assert into some hardware structure?
• 79: Create natural vector as a subtype of integer_vector
  • subtype natural_vector is integer_vector (range 0 to integer'right) ;
  • Good idea, but is it important enough for this revision?
  • How is the range of the elements differentiated from the range of the integer_vector?
  • Does it need to be:
    • subtype natural_vector is integer_vector (<>) (range 0 to integer'right) ;
    • subtype natural_vector is integer_vector ((range 0 to integer'right)) ;
  • Someday maybe
• 80: Inconsistent capitialization of IEEE packages
  • meeting consensus lower case is preferred
  • Someday maybe. Anyone interested.
• 81: Deferred Shared Variables
  • Some vendors have already implemented this via tool settings without use of a new keyword
  • see link to stack overflow discussion
  • AI: Brent to research LRM to identify needed changes if any.
• 82: Implicit Conversions between integer and unsigned/signed, and real and ufixed, sfixed, float
  • Consider with the unbounded integer proposals?
• 83: Syntax Regularization: Empty Records
  • Push to interface proposal
  • Example: Record with debug ports. Some implementations use it. Final version does not.
• 84: Architecture Generic
  • Interesting. Requires architecture name passed as some sort of object
  • Seems that configurations, if synthesizable, solves this problem
• 85: Simulation Controls
  • Need something actionable in the proposal

Review and Approve Meeting Minutes:

Brent, Lieven

Next Meeting: Thursday June 2, 2016, 11 am Pacific

Previous Meeting: Thursday May 19, 2016