P1076 June 2, 2016 Meeting Minutes

Attendees:

• Brent Hayhoe, Rob Gaddi, Jim Lewis, Kevin Jennings, Lieven Lemiengre

Agenda:

Meeting Discussion

• Review PrivateDocuments file: _summary_vhdl_requirements_priority.xlsx
• Restart at line 86
• 86: Additional Rules for Bit String Literals
  • Any value to this?
  • Enhanced error detection?
  • Why " in a bit string literal? No fundamental reason for this.
• 87: All Interface Lists Can Be Ordered
  • Support, however, how much work is it to make the change?
  • Anyone willing to work on this?
  • Since it is already true for Generics, it make sense.
• 88 The Sensitivity List for Process(all) Should Not Include Signals in All Reachable Subprograms
  • Depends on body of package. Will not know this at compile time. Will only know this at elaboration time.
  • Agree to mark it erroneous, given that erroneous means that it is an error to use, but a compiler is not obligated to detect it.
  • Action in LRM: change the word error to erroneous.
• 89 Multiple Design Hierarchies
  • This seems to want to specify elaboration order of two separate designs loaded via a simulator command line.
  • Can the LRM even speak to this? Or is this a tool thing?
  • Need clear explanation of use model and someone to work on it.
• 90 Preponed Process
  • Deals with clock, data delta cycle races.
  • Would modify the execution model of VHDL.
  • AI: get feedback from Tristan
• 91 Update std_logic_arith
  • To maintain backward compatibility would only consider part 1
  • need champion to go anywhere
• 92 Dynamic Process Instance
  • Would be a significant amount of work.
  • With a static number of processes. Use resolved signal to create a barrier synchronization.
  • Lieven envisions we could have something better, but we would need a champion
  • some day maybe
  • need use cases
• 93 Shorthand Subprogram Declarations
  • Some day maybe

Review and Approve Meeting Minutes:

Lieven, Rob, Kevin

Next Meeting: Thursday June 9, 2016, 11 am Pacific

Previous Meeting: Thursday May 26, 2016