P1076 February 11, 2016 Meeting Minutes

Attendees:

• Brent Hayhoe, Patrick Lehmann, Peter Flake, Rob Gaddi, Jim Lewis, Jing Pang, Ernst Christen, Ryan Hinton

Agenda:

Meeting Discussion

• What's Next - see PrivateDocuments file: _summary_vhdl_requirements_priority.xlsx
• Sizing from initial values
  • Seems like something easy to implement
• TextIO Boolean Write
  • Conclusion: Use VHDL-2008 rules and make no change
• DPI - Direct Programming Interface
  • OS dependent? Linking and such will be, however,
  • this proposal identifies what we need to link to
  • Needs someone on the implementation side to identify what is missing
  • AI: Jim to reach out to GHDL group about reviewing and ?early implementation?
• Relax library requirement on configurations
  • Do we know the origins of this restriction
  • Proposal originated from a vendor and they indicated they are already implementing
• FileIO for RTL ROM
  • Package - open source. PoC library has functions for this.
  • How does something like this get accepted by synthesis tools
  • See: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/mem.pkg.vhdl
• Hierarchical Libraries
  • Organize large project libraries
  • Seems like it should be low cost
  • See: https://github.com/VLSI-EDA/PoC/wiki/SubnamespaceTree
• Read Differences between bit_vector and std_ulogic_vector
  • Conclusion: fix std_ulogic_vector to match bit_vector
• to_string/image for composites (line 13) was: Extend IMAGE attribute to arrays and records
  • Hot topic for VHDL
  • Best if predefined.
  • Easy if support #17, Anonymous types on interfaces and introspection (iterate across field names)
• External names for types
  • Useful for statemachines
  • The consequence of not having it would mean moving the type a package.
  • Consequences for compiling a design? Requires one entity compiled before other. Results in secondary architecture (testbench) being dependent on architecture. What if there are multiple architecture and type is different in different architectures.
  • What is exported with the type? Do enumeration literals also come along?
  • Use case for RAMs. type Ram_t is array () of some_type_nn_slv ; signal Ram : ram_t ;
• Updates to standard packages
  • Would be helpful to have all of this on GitHub!
  • Maybe we need to explore costing with GitHub
  • Check in again with Stan. 1076.1 would also benefit from such a account.
• AI: Jim Update links in xlsx file.

Review and Approve Meeting Minutes:

• Rob, Ernst

Next Meeting: Thursday February 18, 2016 11 am Pacific

Previous Meeting: Thursday February 4, 2016