Jim 100 : for 1076.1: DOMAIN_TYPE missing in 3.1.1.1
95- marked as invalid
Chucks concerns are that: A xnor B xnor C /= xnor(A,B,C).
And for xnor reduction operations, xnor A(2 downto 0) = not xor A(2 downto 0) and is not the same as A(2) xnor A(1) xnor A(0).
If one interprets xnor A(2 downto 0) as a 3 input xnor gate this exactly matches how hardware and Verilog works, and hence, the VHDL-2008 impementation is ok.
83 Marked as fixed: LRM was fixed as described in Peter's last paragraph.