P1076 October 24, 2013 Meeting Minutes
Attendees:
Agenda:
ISAC Action Item Review
- Next Meeting: Cliff: IR 2054 & 2063
- Done: Ryan: Tracking proposal for 2132
- Done: Jim: Tracking proposal for 2130
- Done: Peter: Issue closure and/or Tracking Proposal for 2131
- Action: ?Cliff/Ryan? Proposal for ordered port and parameter lists (like generics).
Ordered Port and Parameter Lists
- Allow for types
- Cliff concerned about using initializers for example:
Port (
a: std_logic_vector(7 downto 0) := (others => 'Z') ;
b : a'subtype := a ;
) ;
- Any concern about unconstrained ports:
Port (
a : std_logic_vector ;
b : a'subtype
) ;
Check for New Bugzillas
- 295 - Allow configurations for entities not in the same library - AI Cliff
- 294 - Force of an out port using mode is improperly defined - AI Jim link proposal from ISAC page to collected requirement list
- 293 - Issue with path_name and instance_name wrt VHDL-2008 generate labels - AI Peter
- 291 - Arrays of protected types - AI Jim Already part of ProtectedTypeUpdates separate arrays and records. separate proposal.
- 290 - Allow access type parameters to methods of a protected type. - AI Jim
- Issue: problematic to allow pointer to internal data structure
- What about textio read and write
- 289 - Context declaration requirements are not uniform - AI Daniel, Cliff
- 288 - bit string literals not correctly defined - AI Daniel
- 287 - process(all) non-parameter signal read error should be er... - AI Cliff
- Resolution: leave it as an error vs. change it to erroneous.
- Would like to understand why the reporter claims difficult to do at elaboration time check
- If the subprogram body has been compiled, will it be checked?
Review and Approve Meeting Minutes:
Next Meeting Date (proposed):
Thursday
November 7, 2013, 8 am Pacific (note US will be off of daylight savings time).
Previous meeting:
Oct 10, 2013
Topic revision: r4 - 2020-02-17 - 15:36:13 -
JimLewis