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(2020-02-17,
JimLewis
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E
dit
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ttach
Links to proposals etc.
Back annotation (fairly language neutral)
Alternative scheme for nettypes (Sysytem Verilog)
VHDL proposals -
P1076.Vhdl2019CollectedRequirements#Proposal_Summary_Link_to_Proposa
C++ Extension (if you are fed up with EDA companies) -
http://parallel.cc
--
Kevin Cameron - 2016-03-11
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Topic revision: r3 - 2020-02-17 - 15:34:49 -
JimLewis
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