Bundles As (Kind Of) Entities
Defining the Bundle
bundle qspi is
generic (
CHIP_SELECTS : positive
);
port qmaster (
mosi : out std_logic_vector(3 downto 0);
miso : in std_logic_vector(3 downto 0);
sclk : out std_logic;
cs : out std_logic_vector(CHIP_SELECTS-1 downto 0)
);
port qslave (
generic (
SELECT : integer range 0 to CHIP_SELECTS-1
);
mosi : in std_logic_vector(3 downto 0);
miso : out std_logic_vector(3 downto 0);
sclk : in std_logic;
cs : in std_logic
);
port sslave (
generic (
SELECT : integer range 0 to CHIP_SELECTS-1
);
mosi : in std_logic;
miso : out std_logic;
sclk : in std_logic;
cs : in std_logic
);
signal mosi : std_logic_vector(3 downto 0);
signal miso : std_logic_vector(3 downto 0);
signal sclk : std_logic;
signal cs : std_logic_vector(CHIP_SELECTS-1 downto 0)
end bundle qspi;
bundle body qspi is
port map qmaster (
mosi => mosi,
miso => miso,
sclk => sclk,
cs => cs
);
port map qslave (
mosi => mosi,
miso => miso,
sclk => sclk,
cs => cs(SELECT)
);
port map sslave (
mosi => mosi(0),
miso => miso(0),
sclk => sclk,
cs => cs(SELECT)
);
end bundle body qspi;
Using the Bundle on an Entity
entity cpu is
port (
bundle spi : qspi.qmaster generic map (CHIP_SELECTS => 4);
...
);
end entity cpu;
architecture Behavioral of cpu is
begin
SPI_MASTER: process(clk, rst)
begin
if rst then
spi.cs <= (others => '1');
spi.sclk <= '0';
spi.mosi <= (others => '0');
elsif rising_edge(clk) then
...
end process SPI_MASTER
end architecture Behavioral;
Using the Bundle at Top Level
architecture foo of bar is
bundle qspi generic map (CHIP_SELECTS=>4);
begin
CPU: entity work.cpu
port map (
spi => qspi.qmaster,
...blahblahblah...
)
FLASH : entity work.qspi_flash
port map (
spi => qspi.qslave generic map(SELECT=>0),
);
DAC : entity work.dac
port map (
spi => qspi.sslave generic map(SELECT => 1),
);
end architecture foo;
--
Rob Gaddi - 2016-04-21
Comments
Topic revision: r1 - 2016-04-21 - 19:46:04 -
RobGaddi